`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:53:51 07/02/2014
// Design Name:   apb_slave
// Module Name:   C:/Users/Katerina/Desktop/Mathimata/apb_slave/tb_apb_slave.v
// Project Name:  apb_slave
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: apb_slave
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

`include  "apb_slave.v"

`include  "apb_slave_mem.v"


module tb_apb_slave;

	// Inputs
	reg clk;
	reg reset;
	reg psel;
	reg penable;
	reg pwrite;
	reg [15:0] paddr;
	reg [31:0] pwdata;

	// Outputs
	wire [31:0] prdata;
	wire pslverr;
	wire pready;
	reg [2:0] timeToComplete;
	

	// Instantiate the Unit Under Test (UUT)
	apb_slave uut (
		.clk(clk), 
		.reset(reset), 
		.psel(psel), 
		.penable(penable), 
		.pwrite(pwrite), 
		.paddr(paddr), 
		.pwdata(pwdata), 
		.prdata(prdata), 
		.pslverr(pslverr), 
		.pready(pready)
	);

	initial begin
		// Initialize Inputs
	  $dumpfile("waveform.vcd");
	  $dumpvars(0,tb_apb_slave);
		clk = 0;
		reset = 0;
		psel = 0;
		penable = 0;
		pwrite = 0;
		paddr = 0;
		pwdata = 0;
		timeToComplete = 0;

		// Wait 10 ns for global reset to finish
      #10; 
		
		// Add stimulus here
		reset = 1;
		#60;
		reset = 0;
		
		#1000 $finish;
	end
	
	always #10 clk = ~clk;  //period 20ns
	
	always @(posedge clk or posedge reset) 
	begin
		if (reset) begin
			timeToComplete = 0;
			psel = 0;
			penable = 0;
			paddr = 0;
			pwdata = 32'h00008000;
			pwrite = 1;
		end
		else if (timeToComplete == 2) begin
			timeToComplete = 0;
			psel = 0;
			penable = 0;
			if (pwrite) pwdata = pwdata + 1;
			paddr = paddr + 1;
			if (paddr == 5) begin
				paddr = 0;
				pwrite = 0;
			end
		end
		else if (timeToComplete == 0) begin
			timeToComplete = timeToComplete + 1;
			psel = 1;
		end
		else begin
			timeToComplete = timeToComplete + 1;
			penable = 1;
		end	
	end			
		
endmodule

